In a conventional 0.18 micron logic 1.8V/3.3V silicon-on-insulator (SOI) process, a 0.18 micron logic process is usually used in the back end process. However, through experimental study, the inventor finds that a larger number of mobile ions are generated during the back end process. These mobile ions can conduct along the metal lead, the via, and the intermetallic film, and accumulate at the Si—SiO2 interface, the polysilicon (Poly) edge and the like, which influences the interface state. For the ordinary bulk silicon process, these mobile ions can be discharged out of the substrate, such that the accumulative phenomenon is not obvious. However, for the SOI process, due to presence of buried layer oxidation, the mobile ions cannot be discharged. Therefore, the device can be influenced obviously, which may easily cause disadvantages of gate oxide (GOX), junction or Poly edge. In evaluation of gate oxide layer integrity (GOI), GOI fail occurs.